Frequency divider circuit system

ABSTRACT

A frequency divider wherein the pulse input having been delayed by a predetermined time interval is impressed upon a plurality of cascade connected flip-flops, and the output from each of the flip-flops is fed to an AND gate to which is also fed the input which has not passed through the delay circuit to produce a resultant AND output to be fed back to each of the required flipflops, thereby increasing the upper limit of the frequency to be divided and practically eliminating the danger of a malfunction in the system.

United States Patent Yoshino et a].

451 May 2,1972

[54] FREQUENCY DIVIDER CIRCUIT 22 Filed: Dec. 18,1969

[21] AppLNo; 886,131

[52] US. Cl ..328/l5, 328/42, 328/48,

328/39 51 Int. Cl. 1103b 19/00 [58] Field ofSearch..328/15,42,48,39,25-30, 328/49; 307/225, 226; 331/51 [56] ReferencesCited UNITED STATES PATENTS 2,924,816 2/1960 Schreiber ..328/423,041,476 6/1962 Parker.... ....328/42 3.064890 11/1962 Butler.........328/42 3.076.601 2/1963 Goetz .328/42 3.212.010 10/1965 Podlesny..307/325 3.268.740 8/1966 Rywak ..328/42 INPUT CONTROL INPU T 3,300,7241/1967 Cutair 328/48 3,369,183 2/1968 Mesterm, .328/48 3,408,595 10/1968Hillman 307/227 3,518,553 6/1970 l-lo et a1. ..328/48 OTHER PUBLICATlONSArithmetic Operations in Digital Computers," Richards Nostrand CompanyNJ 2- 55 (p. 195- 197) Schmookler, Delay Free Counter IBM Tech.Disclosur Bull. (p. 929- 932) Vol. 7 No. 10 March 1965 PrimaryExaminer-Donald D. Forrer Assistant Examiner-12. E Hart Atl0rImv-Stevens, Davis, Miller & Mosher [57] ABSTRACT A frequency dividerwherein the pulse input having been delayed by a predetermined timeinterval is impressed upon a plurality of cascade connected flip flops,and the output from each of the flip-flops is fed to an AND gate towhich is also fed the input which has not passed through the delaycircuit to produce a resultant AND output to be fed back to each of therequired flip-flops, thereby increasing the upper limit of the frequencyto be divided and practically eliminating the danger ofa malfunction inthe system.

3 Claims, 7 Drawing Figures PATENTEDMAY 2 I972 3,660,767

saw 2 BF 3 INPUT CONTROL INPUT ILJLJLHJLJTJULI'LJLJL PATENTEDMAY 21972SHEET 3 BF 3 l/vPur Q FREQUENCY DIVIDER CIRCUIT SYSTEM Thisinvention'relates to frequency dividers having flipflops.

In prior art binary feed-back type frequency dividers the time requiredfor input pulses to propagate through a long counter chain resulted in atime lag of the output feed-back pulse from the last stage fordetermining the frequency dividing ration behind the corresponding inputpulse.

Therefore, when the frequency dividing ratio is an odd number, theoutput feed-back pulse is impressed upon the first stage to increase theresolving time of the flip-flop of this stage, which increases thepossibility of a malfunctioning for inputs of higher repetitionfrequencies. When the time lag of the feed-back pulse is extremelyshort, either one of the input pulse and the feed-back pulse whichoccasionally coincides with the input pulse at a stage is disregarded bythe flip-flop of that stage to result in a malfunction. This isdiscussed in connection with a prior art frequency divider circuit shownin FIG. 1. Flip-flops F F F F and F, are connected in cascade andswitches R R R R are provided in the feed-back circuits for therespective flip-flops. By appropriate operation of the switches, thefeed-back pulse from the last stage F, is selectively impressed uponeach stage to determine the frequency dividing ratio of the frequencydivider. It is desirable for the appearance of the output feed-backpulse i,, to lag behind a pulse which appears 2" cycles after the inputpulse i, by an interval which is less than one period of the input pulsetrain. Actually, i lags i by a dead time t,,= nAt, where A! is a timelag for each of the flip-flop stages F to F,,. Thus, when the switch Ris closed, the lagging feed-back pulse i,,,, occasions the pulse timingshown at (a), (b) and (c) in FIG. 3, with the pulse period of the inputpulse signal being l/fl, for a repetition frequencyf The smaller t l/fis, the higher is the resolution of the first-stage flip-flop that isrequired. The resolution herein refers to a minimum value of the pulseperiod for the proper functioning of the flip-flop.

Influence of the time lag of 1",, is most pronounced at the first stage,and the second and the third stages will also be influenced if the timelag is greater than l/fl,, or if the repetition frequency of the inputpulse signal is increased, thus causing malfunctioning. Also, thegreater the number of flip-flop stages, the more the time lag of i isincreased to promote malfunctioning. Thus, the upper limit of thefrequency to be divided depends upon the switching and delay time foreach flip-flop and is decreased with an increasing number of stages.

The foregoing will be seen from FIG. 3. At (a) of FIG. 3 is shown thecase where the delay time of the feed-back pulse from the last stageexceeds the pulse period of the input, at (b) is shown the case wherethe delay time is less than the pulse period, and at (c) is shown thecase with the shortest delay time, for which the resolution is thehighest.

An object of the present invention, accordingly, is to provide afrequency divider which will not be subject to malfunctioning, even withhighly repetitive input signal pulses. Another object of the inventionis to provide a variable frequency divider wherein the obtained controlpulse is used as the feed-back pulse. A further object of the inventionis to provide frequency divider capable of high-speed carry by using theobtained control pulse as the carry pulse.

The invention will now be described in conjunction with the preferredembodiments thereof with reference to the accompanying drawing, inwhich:

FIG. 1 is a block diagram of a prior art feed-back type frequencydivider;

FIG. 2 is a timing chart of the pulses involve in the system shown inFIG. 1;

FIG. 3 is a timing chart showing the influence of the delay involved inthe system of FIG. 1; 1

FIG. 4 is a block diagram of one embodiment of the variable frequencydivider according to the invention;

FIG. 5 is a timing chart of the pulses involved in the system shown inFIG. 4;

FIG. 6 is a block diagram of another embodiment of the frequency dividercapable of high-speed operation in accordance with the invention; and

FIG. 7 is a timing chart involved in the system shown in FIG. 6.

According to the features of the invention there is provided a frequencydivider comprising a delay circuit for delaying the input signal, acounter circuit including a plurality of flip-flops connected incascade, and an AND circuit for forming the logical product of theoutput from each of the flip-flops and the non-delayed input signal.Referring now to the drawing, particularly to FIG. 4 showing a preferredembodiment of the invention, the input signal is fed through a delaycircuit T to flipflops F to F, connected in cascade and individuallyconstituting the respective stages of the counter circuit. The outputfrom each of the stages is fed to an AND gate 6 to which is also fed thenon-delayed input to produce an AND output to be fed through acorresponding one of the gate circuits R to R,, back to each of therespective stages. A frequency dividing ratio setting circuit H controlsthe on-or-ofi' function of the gates R to R,, in accordance with thecontrol input. In FIG. 5, at (a) are shown the input pulses, at (b) areshown the input pulses having passed through the delay circuit T, and at(c), (d), (e) and (f) are shown outputs from the respective flipflops FF F and F At the AND gate G is available a pulse output shown at (g).

The flip-flops F F and F are provided with associated AND gates G G and6;, so as to gate these flip-flops respectively from the previous stageflip-flops and actuate flip-flops F, F and F by the delayed inputsignal, so that the delay time for each of them is constant all throughat At. However, for the next stage F and so on the delay time isprogressively increased to 2A1, 3At,

As is seen, the provision of the AND gate G has the effect thatnotwithstanding the great time lag of i behind i,,, the pulse outputfrom the gate G leads in its timing with respectto an input clock pulseappearing out of the delay circuit T 2" cycles after the input pulsecorresponding to the feed-back pulse i by a time interval prescribed bythe delay circuit, so that the situations shown at (a) and (b) in FIG. 3will never take place and malfunctioning is absolutely eliminated.

For the situation as shown at (c) in FIG. 3, i.e., without the delaycircuitT, a feed-back pulse and an input pulse will happen to becompletely coincident at one of the cascade connected stages in thecounter chain; that is, the two pulses will happen to be simultaneouslyimpressed upon one flip-flop. As a result, one of the impressed pulsesis disregarded by the flipflop, which is thus forced to assume either aset or a re-set stable state, whereby either one or both of the statesof both the input and feed-back pulses previous to their entry into theflipflop in question are interrupted as in i at (c) in FIG. 3, thusresulting in malfunctioning of the counter chain. In practice theflip-flop in each stage should be responsive to both input and feed-backpulses so as to keep their state before their impression upon thefollowing stage from being accidentally interrupted.

In the system according to the invention the feed-back pulse to eachstage suitably leads the input pulse to that stage as shown at (a) to(g) inclusive in FIG. 3, so that there is no possibility of coincidenceof both pulses giving rise to malfunctioning.

It will also be apparent from that shown at (h) to (l) inclusive in FIG.5 that the delay circuit T makes it possible to eliminate malfunctioningof the system which would otherwise occur as a result of doubling anequivalent feed-back pulse,

output from the flip-flop F, the output from the AND gate G of thesystem without the delay circuit T, and the output from the AND gate Gof the system having the delay circuit T.

FIG. 6 shows another embodiment of the invention, with FIG. 7illustrating the timing involved. It enables high-speed decimal carry byfeeding the output from the flip-flop F the output from flip-flop F andthe input to AND gate G whose output triggers flip-flop F thus reducingthe delay occurring through the cascade connection of the decimalcounter circuits.

In FIG. 7, at (a) is shown the input, at (b) is shown the input havingpassed through delay circuit T, at (c) is shown the output fromflip-flop F at (d), (e) and (f) are shown the respective outputs fromflip flop F F and F,,, at (g) is shown the output from AND gate G of thesystem without delay circuit T, and at (h) is shown the output from ANDgate T of the system provided with a delay circuit T. Without the delaycircuit T, the pulse signal shown at (b) in FIG. 7 is subject to gatingwith the signals shown at (c) and (f), so that satisfactory carry pulsescannot be obtained, as is shown at (g) in FIG. 7. On the other hand,with the delay circuit the pulse signal shown at (a) in FIG. 7 issubject to gating with the signals shown at (c) and (f) in FIG. 7, sothat satisfactory carry pulses can be obtained.

As has been described in the foregoing by-the provision of an ANDcircuit and delay circuit it is possible to have a frequency dividerpractically free from any malfunctioning.

' What is claimed is:

1. A frequency divider, comprising:

means, including a delay circuit, for delaying an input pulse signalapplied to said frequency divider;

a counter circuit including a plurality of cascade connected meansapplying the delayed input pulse signal to at least a portion of saidplurality of flip-flops;

means, including an AND circuit for producing an AND product of thenon-delayed input pulse signal and the outputs of said plurality offlip-flops; and

means, including a plurality of gate circuits, each connected to acorresponding one of said plurality of flip-flops, for selectivelyapplying the output of said AND circuit to said corresponding one ofsaid plurality of flip-flops.

2. A frequency divider according to claim 1, further comprising a secondAND circuit, having said delayed input pulse signal as a first input andthe output of a first of said cascade connected flip-flops as a secondinput, the output of said second AND circuit being connected to theinput of a second of said cascade connected flip-flops.

3. A frequency divider, comprising:

means, including a delay circuit, for delaying an input pulse signal;

a first counter circuit including a plurality of cascade conmeansapplying the delayed input pulse signal to at least a portion of saidplurality of flip-flops;

a second counter circuit including at least one flip-flop;

means, including an AND circuit, for producing an AND product of thenon-delayed input pulse signal and the output of said first countercircuit; and means applying the output of said AND circuit to the inputof said second counter circuit.

1. A frequency divider, comprising: means, including a delay circuit,for delaying an input pulse signal applied to said frequency divider; acounter circuit including a plurality of cascade connected flip-flops;means applying the delayed input pulse signal to at least a portion ofsaid plurality of flip-flops; means, including an AND circuit forproducing an AND product of the non-delayed input pulse signal and theoutputs of said plurality of flip-flops; and means, including aplurality of gate circuits, each connected to a corresponding one ofsaid plurality of flip-flops, for selectively applying the output ofsaid AND circuit to said corresponding one of said plurality offlip-flops.
 2. A frequency divider according to claim 1, furthercomprising a second AND circuit, having said delayed input pulse signalas a first input and the output of a first of said cascade connectedflip-flops as a second input, the output of said second AND circuitbeing connected to the input of a second of said cascade connectedflip-flops.
 3. A frequency divider, comprising: means, including a delaycircuit, for delaying an input pulse signal; a first counter circuitincluding a plurality of cascade connected flip-flops; means applyingthe delayed input pulse signal to at least a portion of said pluralityof flip-flops; a second counter circuit including at least oneflip-flop; means, including an AND circuit, for producing an AND productof the non-delayed input pulse signal and the output of said firstcounter circuit; and means applying the output of said AND circuit tothe input of said second counter circuit.